Semiconductor technologies are continually progressing to smaller feature sizes, for example down to feature sizes of 28 nanometers, 20 nanometers, and below. A patterned photoresist (PR) layer used to produce such small feature sizes typically has a high aspect ratio. Maintaining a desired critical dimension (CD) can be very difficult for various reasons, including incapability of shrinking the minimum area and degraded trench end resolution. Multiple patterning is used to enhance the lithography patterning resolution. However, the mask alignments associated with multiple patterning has various difficulties that include mask alignment conflicts, especially between different layers.
Therefore, what is needed is a method and a system to provide effective IC design and fabrication for the advanced IC technologies addressing the above issues.